Optic Flow Sensor for Artificial Compound Eyes

Miniaturized low-power artificial compound eyes in a small form factor and a low payload can be a promising approach to provide wide-field information for micro-air-vehicle (MAV) applications. Recently, research efforts have been made to realize bio-inspired artificial compound eyes to mimic the wide field of view (FoV) of insect visual organs by implementing photoreceptors to independently face different angles [1-2]. However, these approaches have drawbacks. They use complicated fabrication processes to form a hemispherical lens configuration and secure an independent optical path to each photoreceptor. We take a simple and practical approach to realize wide-field optic flow sensing in a pseudo-hemispherical configuration by mounting a number of 2D array optic flow sensors on a flexible PCB module as shown in Figure 7.2.1. In this scheme, the 2D optic flow sensor should meet the requirements of MAV applications: extremely low power consumption while maintaining robust optic flow generation. Conventional optic flow algorithms, such as Lucas-and-Kanade, require huge amounts of numerical calculations; therefore, they require substantial digital hardware (CPU and/or FPGA), resulting in large power consumption [3-4]. As an alternative approach for low-power implementation, bio-inspired elementary motion detector (EMD) based algorithms (or neuromorphic algorithms) have been studied and implemented in analog VLSI circuits for autonomous navigation [5-6]. However, pure analog signal processing is easily susceptible to temperature and process variations and it is difficult to scale the pixel size or apply low-power design techniques because extensive analog processing is implemented in pixel-level circuits. In this work, we have devised and implemented a time-stamp-based optic flow algorithm, which is modified from the conventional EMD algorithm to give an optimum partitioning of hardware blocks in analog and digital domains as well as assign adequate allocation of pixel-level, column-parallel, and chip-level processing. Temporal filtering, which may require huge hardware resources if implemented in the digital domain, remains in a pixel-level analog processing unit. Feature detection is implemented using digital circuits that are column parallel. The embedded digital core decodes the 2D time-stamp information into velocity using chip-level processing. Finally, the estimated 16b optic flow data are compressed and transmitted to the host through a 4-wired Serial Peripheral Interface (SPI) bus.